FIG. 7 is a flow chart of a manufacturing process for producing a flip-chip IC as a semiconductor integrated circuit package according to a prior art tape automated bonding (hereinafter referred to as TAB) technique. The technique illustrated in FIG. 7 includes inner lead bonding (hereinafter referred to as ILB) and outer lead bonding (hereinafter referred to as OLB). FIGS. 8(a)-8(e) are diagrams illustrating the flow of ILB and OLB in the manufacturing process of FIG. 7.
In the figures, reference numeral 1 designates an IC chip. Bumps 2 disposed on the IC chip 1 are terminals for ILB. A polyimide film carrier 4 for bonding to the IC chip 1 has inner leads 3 at its inner ends. A resin 5 is deposited on the rear surface of the IC chip 1 including the bonded portions between the bumps 2 and the inner leads 3. A printed circuit board 6 is provided for mounting of the IC chip 1 via a lead frame 3'. Wiring electrodes 7 are located on the printed circuit board 6. The lead frame 3' constituting the outer lead portions is fixed to the wiring electrode 7 on the printed circuit board 6 with solder 8.
After semiconductor device layers are produced by a wafer process at step S71, electrodes are formed at step S72. Thereafter, a test is carried out in the wafer state at step S73 (wafer test), cutting is carried out at step S74, and chip separation is carried out at step S75. The Au bumps are formed on the electrodes of the IC chip 1 to produce the chip shown in FIG. 8(a). As shown in FIG. 8(b), the inner leads 3 on the polyimide film carrier 4 are thermally adhered, under pressure, to each other, thereby completing a flip-chip ILB at step S76, illustrated in FIG. 8(c).
Plastic molding is carried out at step S77, see FIG. 8(d), hardening is carried out at step S78, and the outer leads (lead frames) 3' are cut by punching and formed into a predetermined size at step S79. Thereafter, a burn-in test is carried out at step S80 and the outer leads 2' are bonded to the wiring substrate 6 with solder 8, as shown in FIG. 8(e), thereby completing the substrate mounting OLB at step S81.
Heretofore, it was required to apply solder to the wiring substrate electrode 7. Methods of bonding and heating include pulse tool heating, constant tool heating, light beam heating, and laser heating. After the substrate mounting OLB is carried out, a test of the device is carried out at step S82.
Since the flip-chip package according to the prior art TAB technique has the above-described structure, in bonding the Au bumps to the Ni-Au gilded inner leads 3 in the ILB process, high temperature and high pressure are required and control of the applied pressure is difficult. When pressure is abruptly applied, the silicon dioxide film below the aluminum electrode of the IC chip 1 is damaged. In addition, the inductance of the lead 3' for the OLB causes deterioration of the IC chip characteristics and the lead is required to be as short as possible. This causes an especially difficult problem in high frequency circuits and high speed switching circuits. When a large current flows in an IC chip and causes heat generation, it is difficult to increase the heat conductivity between heat radiating fins and the IC chip.